BWE=0, CBSY=0, SDD0MON=0, ILW=0, DTO=0, CMDE=0, ILA=0, BRE=0, RSPTO=0, SD_CLK_CTRLEN=0, ENDE=0, CRCE=0, ILR=0
SD Card Interrupt Flag Register 2
| CMDE | Command Error 0 (0): Command error not detected 1 (1): Command error detected |
| CRCE | CRC Error 0 (0): CRC error not detected 1 (1): CRC error detected |
| ENDE | END Error 0 (0): End bit error not detected 1 (1): End bit error detected |
| DTO | Data Timeout 0 (0): Data timeout not detected 1 (1): Data timeout detected |
| ILW | SD_BUF Illegal Write Access 0 (0): Illegal write access to the SD_BUF register not detected 1 (1): Illegal write access to the SD_BUF register detected |
| ILR | SD_BUF Illegal Read Access 0 (0): Illegal read access to the SD_BUF register not detected 1 (1): Illegal read access to the SD_BUF register detected |
| RSPTO | Response Timeout 0 (0): Response timeout not detected 1 (1): Response timeout detected |
| SDD0MON | SDDAT0Indicates the SDDAT0 state of the port specified by SD_PORTSEL. 0 (0): SDDAT0 is set to 0. 1 (1): SDDAT0 is set to 1. |
| BRE | SD_BUF Read Enable 0 (0): Data cannot be read from SD_BUF0. 1 (1): Data can be read from SD_BUF0. |
| BWE | SD_BUF Write Enable 0 (0): Data cannot be written in SD_BUF0. 1 (1): Data can be written in SD_BUF0. |
| SD_CLK_CTRLEN | When a command sequence is started by writing to SD_CMD, the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN bit is set to 0. The SCLKDIVEN bit is set to 1 after 8 cycles of SDCLK have elapsed after setting of the CBSY bit to 0 due to completion of the command sequence. 0 (0): The SD/MMC bus (CMD, DAT) is busy. Writing to the SCLKEN and DIV bits in SD_CLK_CTRL is not possible. 1 (1): The SD/MMC bus (CMD, DAT) is not busy. |
| CBSY | Command Type Register Busy 0 (0): A command sequence is being executed. 1 (1): A command sequence has been completed. |
| ILA | Illegal Access Error 0 (0): Illegal access error not detected 1 (1): Illegal access error detected |